Applicants own Swedish patent SE-0300784-6 (publication No. 526 366) discloses and claims through connections (also referred to as vias) made in a wafer material from the native wafer itself. The vias thereby comprises the same material as the remainder of the wafer and will thus be capable of being processed in a more versatile manner, as describe in detail in said application, the disclosure of which is incorporated herein in its entirety by reference.
However, for certain applications the resistivity that is attainable in these prior art vias may be too high, and it would be desirable to provide vias with very low resistivity.
It is known to provide vias made of metal, but the conventional methods used (sputtering, plating, or evaporation methods) are all suffering from the problem that it is difficult to fill very small holes with them without getting voids.
In U.S. Pat. No. 5,654,232 (Gardner) there is disclosed a method of making an electrical interconnection by melting copper into recesses or grooves made in a dielectric layer on a semi-conductor substrate. The prior art process according to U.S. Pat. No. 5,654,232 comprises making a recess in a dielectric layer which is provided on a semi-conductor substrate, and by providing a wetting-layer allowing copper metal to fill the recess. The recesses are comparatively shallow and do not extend through the wafer.
Other disclosures relating to this technology is to be found i.a. in US20040187975 (Tatsuo et al), 20030119 (Yamamoto), US20040043615 (Satoshi et al), U.S. Pat. No. 6,002,177 (Gaynes et al), US2005023675 (Mitsuo et al), US20010045654 (Givens), US20050801 (Leung) and US20050801 (Hara).
In the industry there is a strive to make component and wafer stacking as compact as possible, and improvements in via technology are therefore sought for.